TBV raises the level of verification abstraction away from a wire-level interface to run thousands to a million times faster than simulation on a host PC. This transaction-level interface allows the testbench to be tightly or loosely coupled to the DUT. A JTAG transactor is used for collecting debug data from the whole system. The Transactor is responsible for converting the high-level HVL commands into low-level DUT pin wiggles (HDL), and handling the communication between the two domains (HVL and HDL) (Figure 2) [16], [17]. The co-emulation infrastructure abstracts away the details of the communi-cation channel linking the testbench to the emulation platform. So, as an example, the BFM would receive the high-level transaction command “read file” from the channel and convert it to the precise, cycle-accurate, wire-level handshake sequences that a physical direct memory access (DMA) controller, located within the emulated DUT, would need. Vendors and users provide libraries of transactors for standard interface protocols as well as tools to enable the development of custom, proprietary transactors. It finally gave design teams access to the full performance of the emulator without sacrificing much, if any, of the flexibility/visibility of simulation. A hardware-based domain, or HDL domain, running in the emulator, and a software-based, or hardware verification language (HVL) domain, executes on the host computer. Our SoC can now boot up an operating system which is loaded through the USB transactor. Co-emulation offers several advantages over ICE. He holds a bachelor’s degree in engineering from California Polytechnic State University, San Luis Obispo, and a master’s degree in business administration from Santa Clara University, Santa Clara, Calif. https://www.facebook.com/ElectronicDesign. By adopting accelerated transaction-based emulation strategies, design teams can now move their verification strategy up a level of abstraction and achieve the leap forward in verification performance and productivity that is necessary to fully debug and develop the most complex electronic hardware and software-based systems. Very few design teams enjoy a project schedule that can accommodate that. With this growth, we’ve seen verification complexity grow exponentially, driving engineers to seek advanced verification methodologies. ICE is not without its challenges, however, as an emulator is rarely fast enough to run at the same speed at which a target system would normally operate. The communication between emulator and workstation can be implemented using SCE-MI based DPI import and export functions and tasks, as well as SCE-MI pipe semantics. The second is that these test benches execute faster than conventional RTL benches, since mapping the bus-functional model (BFM) of the transactor inside the emulator achieves dramatic acceleration. Primarily, it eliminates the need for rate adapters and physical interfaces. Transactors allow the emulator to process data continuously with minimal stalling, dramatically increasing overall performance over PLI-based acceleration, and approaching the performance of ICE. The SmartDV's UART Synthesizable Transactor is fully compliant with standard UART 16550 Specification and provides the following features. Here the transactions are converted to a wire-level interface that interacts with the DUT. Transaction-oriented instead of signal-oriented, leading to much higher speed. The front-end interface is typically a behavioral model that runs on the host PC and interfaces to the testbench, usually through Direct Programming Interface (DPI) calls. Leveraging the emulator’s large reserves of physical memory, designers load this memory with system software, such as firmware, drivers, or an entire OS. Because virtually no simulation testbenches are synthesizable in today’s advanced verification environments, this method is limited in use. Nevertheless, for designs requiring hardware/software co-verification, as well as those utilizing many industry-standard protocol interfaces, maximum verification performance is required. Unlike speed-rate adapters, transactor models for the latest protocols are readily available off-the-shelf and easily upgraded to accommodate protocol revisions. With simulation, the design runs at a wire level and is clock accurate, which means there is a wire-level interface between the testbench and the DUT. The RTL describing this system is loaded into a ZeBu emulator and then connected to a host system. their emulation system by compiling a transactor onto the emulator, in a way similar to the one presented in this paper [18]. It can be time-aware but should not have explicit time-advancement statements like clock or unit delays. It readily fits a methodology like UVM since UVM has largely the same layering principles. This approach also enables greater reuse of System Verilog and UVM-based testbenches and testbench components to build emulation-specific tests. SoCs now include many industry-standard interfaces, multiple processor cores, on-board memories, and embedded firmware and software. With co-simulation, also called simulation acceleration, the DUT is moved to the high-performance emulator as with the other use models. To do this, first the DUT is moved from the host PC to dedicated emulation hardware. Platform-portable, emulation-compatible transactors offer a unique combination of performance, accessibility, flexibility, and scalability. SCE-MI is a set of modeling APIs between behavioral models running on a workstation and synthesisable HDL models running on an emulator. Transactor. Perhaps more interestingly is the verification technology that Synopsys has intetgrated in with the Eve emulation technology they acquired. Conceptually, this verification approach is very straightforward as it leverages the existing simulation testbench and eliminates the need for external rate adapters. It’s also possible to create an emulation-like environment by using transactors to connect the DUT to “virtual devices.” A virtual device is a software model of a peripheral device that runs on the workstation. No more “spaghetti cables!”. Emulation Setup The entire SOC is emulated on a ZeBu-UF 0.5 and interacts with the outside world through two transactors. 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